1. Field of the Invention
The present invention generally relates to the field of microprocessors and more particularly to a microprocessor including a performance monitor unit that uses a shared bus in conjunction with dedicated performance events signals to permit the monitoring of a wide variety of performance events while conserving the area of the layout.
2. Description of the Related Art
U.S. Pat. No. 6,718,403 entitled “Hierarchical Selection of Direct and Indirect Counting Events in a Performance Monitoring Unit”, issued Apr. 6, 2004 discloses a microprocessor including a performance monitor unit. The performance monitor unit includes a set of performance monitor counters and a corresponding set of control circuits and programmable control registers. The performance monitor unit receives a first set of event signals from functional units of the processor. Each of the first set of events is routed directly from the appropriate functional unit to the performance monitor unit. The performance monitor unit further receives at least a second set of event signals. In one embodiment, the second set of event signals is received via a performance monitor bus of the processor. The performance monitor bus is typically a shared bus that may receive signals from any of the functional units of the processor. The functional units may include multiplexing circuitry that determines which of the functional units has mastership of the shared bus. Whereas the performance monitor unit is typically capable of monitoring the direct event signals in any of its counters, the indirect event signals may be selectively routed to the counters. The shared bus may be divided into sub-groups or byte lanes where the byte lanes are selectively routed to the set of performance monitor counters. The state of a control register may determine the event that is monitored in the corresponding counter. In one embodiment, the control register provides a set of signals that are connected to the select inputs of one or more multiplexers. The multiplexers receive multiple events signals and, based on the state of their select signals, route one of the received event signals to the corresponding performance monitor counter. Specified states of the select signals may result in the disabling of the corresponding counter or enabling the counter to count system clock cycles rather than any performance event.
Using a byte configurable event bus simplifies the routing of events to the PMU and allows for generic situations within the PMU for dealing with event data. Examples of these generic structures are bit counters (that operate on a single bit within the byte), bit comparators that compare two or more bits, and decoders that operate on multiple bits. These generic structures are powerful but at the same time can be somewhat limiting.
What are needed are flexible structures for counting and decoding patterns of bits within a byte for a performance monitor counter.